SOURCE: STATS ChipPAC

STATS ChipPAC

January 17, 2011 16:00 ET

STATS ChipPAC Expands Wafer Level Package Offering With 300mm Manufacturing in Taiwan

300mm Wafer Level Packaging Increases Available Capacity With Additional Technology and Cost Advantages

SINGAPORE - 1/18/2011, UNITED STATES--(Marketwire - January 17, 2011) - STATS ChipPAC Ltd. ("STATS ChipPAC" or the "Company") (SGX-ST: STATSChP), a leading semiconductor test and advanced packaging service provider, today announced the expansion of its wafer level package (WLP) offering with new 300mm manufacturing capabilities in Taiwan. The 300mm WLP operation is synergistically located in Hsin-chu Hsien in proximity to the world's leading wafer foundries and supplements the Company's current 300mm wafer bumping operation. The 300mm WLP offering also notably includes a number of new process technologies such as low cure temperature polymers and the use of copper for under bump metallization (UBM) and redistribution layers (RDL) to achieve higher densities and increased package reliability.

Wafer level packages differ from laminate and leadframe based packages in that all of the manufacturing process steps are performed in parallel at the silicon wafer level rather than sequentially on individual semiconductor chips. As a result, a wafer level chip scale package (WLCSP) is essentially the same size as the die, providing a more compact package footprint than conventional manufacturing processes.

"Wafer level packaging has been one of the fastest growing package types in the industry with demand that has outpaced the available market capacity. As a small, lightweight, high performance semiconductor solution, WLCSP is a compelling, cost effective solution for space constrained mobile applications," said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC. "The expansion of our 300mm wafer level packaging is important because it provides a significant increase in total available capacity for our customers and allows us to drive higher efficiencies and economy of scale in our wafer level processes for more cost effective packaging solutions."

With wafer level packaging, the cost per package is primarily determined by the number of die per wafer rather than the number of input/output (I/O) per device. STATS ChipPAC has benefited from a successful production ramp up in wafer level packaging and has more than doubled its production volume in Asia since 2009. The expansion to the larger scale 300mm wafers for WLP reinforces STATS ChipPAC's commitment to deliver production capacity and capabilities in strategic locations to service its customers with full turnkey WLCSP assembly and test services for both 200mm and 300mm wafer sizes.

STATS ChipPAC's new process technologies such as electroplated copper RDL and UBM enable customers to achieve higher densities and increased reliability in their wafer level packages. To support a wider range of applications, the Company has completed qualification on WLCSP body sizes up to 5x5mm with qualification underway for 7x7mm.

Han continued, "The new 300mm wafer level packaging capability in Taiwan is one important facet of our broader wafer level packaging portfolio which includes wafer bump, Fan-Out Wafer Level Chip Scale Packaging (eWLB), Integrated Passive Device (IPD) and Through Silicon Via (TSV) technology."

Forward-Looking Statements
Certain statements in this release, are forward-looking statements that involve a number of risks and uncertainties that could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilization; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; shortages in supply of key components; customer credit risks; disruption of our operations; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or cancelling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; classification of our Company as a passive foreign investment company; our ability to develop and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; majority ownership by Temasek Holdings (Private) Limited ("Temasek") that may result in conflicting interests with Temasek and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; labor union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases, the continued trading and listing of our ordinary shares on the Singapore Exchange Securities Trading Limited ("SGX-ST"); and other risks described from time to time in the Company's filings with the U.S. Securities and Exchange Commission, including its annual report on Form 20-F dated March 5, 2010. You should not unduly rely on such statements. We do not intend, and do not assume any obligation, to update any forward-looking statements to reflect subsequent events or circumstances.

About STATS ChipPAC Ltd.
STATS ChipPAC Ltd. is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. With global headquarters in Singapore, STATS ChipPAC has design, research and development, manufacturing or customer support offices in 10 different countries. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com. Information contained in this website does not constitute a part of this release.

Contact Information

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