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STATS ChipPAC Offers Complete Package on Package (PoP) Solutions With Both Top and Bottom Package Technologies
Flexibility and Scalability of up to 5 Stacked Die in the Top Package Integrates With up to 2 Stacked Die in the Bottom Package
| Source: STATS ChipPAC
UNITED STATES -- (MARKET WIRE) -- January 29, 2007 -- SINGAPORE -- 1/29/2007 -- STATS ChipPAC Ltd.
("STATS ChipPAC" or the "Company") (NASDAQ : STTS ) and (SGX-ST: STATSChP), a
leading independent semiconductor test and advanced packaging service
provider, today announced a complete Package on Package (PoP) solution with
both top and bottom package designs for cell phones, PDAs and other
handheld products. PoP is a three dimensional (3D) package technology in
which two fully-tested packages are stacked during the board mount process
to achieve additional functionality and configuration flexibility with a
minimal increase in size.
The top package of a PoP typically integrates stacked memory devices in a
Fine Pitch Ball Grid Array (FBGA) configuration, while the bottom PoP
package usually contains a logic device or logic device combination (logic
+ logic, logic + analog, etc.). PoP solutions are customized according to
the needs of the end market application and typically have a final package
height of less than 1.6mm. With the ability to mix and match IC
technologies as well as source devices from multiple manufacturing sources,
PoP enables semiconductor companies to quickly respond to changes in market
demand and modify the combination of silicon technology during final board
assembly. STATS ChipPAC is in volume production on both top and bottom PoP
packages.
"PoP continues to gain momentum as a flexible, successful integration
technology which delivers increased device density and functionality in a
smaller footprint to support the needs of the handset market. PoP solutions
enable a lower mounted height approaching 1.4mm for certain package
combinations," said Dr. Han Byung Joon, STATS ChipPAC's Executive Vice
President and Chief Technology Officer. "The ability to offer a single
manufacturing source for both top and bottom packages provides a number of
benefits to our customers, including increased design compatibility,
tightly controlled warpage, increased reliability, and improved board mount
yields."
PoP provides significant versatility in combining top and bottom packages
from different manufacturing sources. However, design compatibility is
paramount to avoid solder reflow quality issues. When top and bottom PoP
packages are stacked on the application board and reflowed together
simultaneously during the surface mount process, high reflow temperatures
can cause thin PoP packages to warp. Therefore, optimization of the
substrate and package design, bill of materials, and assembly process are
key to producing a reliable final solution with high board mount yields.
STATS ChipPAC's bottom PoP package was introduced in 2005 and is currently
in volume production in both single and two die stack versions. The top PoP
package design, integrating up to five stacked die, was qualified in the
fourth quarter of 2006 and has quickly ramped to volume production.
Dr. Han commented, "Customers have the flexibility to mix and match our top
and bottom PoP packages with other manufacturing sources or they have the
benefit of a complete PoP solution from a proven technology leader. Our
goal is to provide the best solution to meet our customer's needs."
About STATS ChipPAC Ltd.
STATS ChipPAC Ltd. ("STATS ChipPAC" or the "Company") (NASDAQ : STTS ) and
(SGX-ST: STATSChP) is a leading service provider of semiconductor packaging
design, assembly, test and distribution solutions. A trusted partner and
supplier to leading semiconductor companies worldwide, STATS ChipPAC
provides fully integrated, multi-site, end-to-end packaging and testing
solutions that bring products to the market faster. Our customers are some
of the largest wafer foundries, integrated device manufacturers (IDMs) and
fabless companies in the United States, Europe and Asia. STATS ChipPAC is a
leader in mixed signal testing and advanced packaging technology for
semiconductors used in diverse end market applications including
communications, power, digital consumer and computing. With advanced
process technology capabilities and a global manufacturing presence
spanning Singapore, South Korea, China, Malaysia and Taiwan, STATS ChipPAC
has a reputation for providing dependable, high quality test and packaging
solutions. The Company's customer support offices are centered in the
United States (California's Silicon Valley, Arizona, Texas, Massachusetts,
Colorado and North Carolina). Our offices outside the United States are
located in South Korea, Singapore, China, Malaysia, Taiwan, Japan, the
Netherlands and United Kingdom. STATS ChipPAC's facilities include those
of its subsidiary, Winstek Semiconductor Corporation, in Hsinchu District,
Taiwan. These facilities offer new product introduction support,
pre-production wafer sort, final test, packaging and other high volume
preparatory services. Together with our research and development centers in
South Korea, Singapore, Malaysia, China, Taiwan and the United States as
well as test facilities in the United States, this forms a global network
providing dedicated test engineering development and product engineering
support for customers from design to volume production. STATS ChipPAC is
listed on both the Nasdaq Stock Market and the Singapore Exchange
Securities Trading Limited. In addition, STATS ChipPAC is also included in
the Morgan Stanley Capital International (MSCI) Index and the Straits Times
Industrial Index. Further information is available at www.statschippac.com.
Information contained in this website does not constitute a part of this
release.
Certain statements in this release, including statements regarding expected
future financial results and industry growth, are forward-looking
statements that involve a number of risks and uncertainties that could
cause actual events or results to differ materially from those described in
this release. Factors that could cause actual results to differ include
general business and economic conditions and the state of the semiconductor
industry; level of competition; demand for end-use applications products
such as communications equipment and personal computers; reliance on a
small group of principal customers; decisions by customers to discontinue
outsourcing of test and packaging services; continued success in
technological innovations; availability of financing; delays in acquiring
or installing new equipment; our substantial level of indebtedness;
potential impairment charges; ability to develop and protect our
intellectual property; intellectual property rights disputes and
litigation; capacity utilization; limitations imposed by our financing
arrangements which may limit our ability to maintain and grow our business;
pricing pressures including declines in average selling prices; changes in
customer order patterns; shortages in supply of key components; disruption
of our operations; loss of key management or other personnel; defects or
malfunctions in our testing equipment or packages; changes in environmental
laws and regulations; exchange rate fluctuations; regulatory approvals for
further investments in our subsidiaries; significant ownership by Temasek
Holdings (Private) Limited (Temasek Holdings) that may result in
conflicting interests with Temasek Holdings and our affiliates; our ability
to successfully integrate the operations of former STATS and ChipPAC and
their employees; labor union problems in South Korea; uncertainties of
conducting business in China; unsuccessful acquisitions and investments in
other companies and businesses; and other risks described from time to time
in the Company's SEC filings, including its annual report on Form 20-F
dated February 28, 2006. We undertake no obligation to publicly update or
revise any forward-looking statements, whether as a result of new
information, future events or otherwise.