Cadence Design Systems, Inc.

August 08, 2011 08:00 ET

Sunplus Technology Picks Cadence Transaction-Level Modeling Flow for Next-Gen Multimedia ICs

Multimedia IC Design Company Speeds Design and Verification Time by Moving to Higher-Abstraction Design

SAN JOSE, CA--(Marketwire - Aug 8, 2011) - Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Sunplus Technology Co., Ltd. (TAIEX: 2401) (LSE: SUPD), a leading multimedia IC design company, adopted the Cadence® transaction-level modeling (TLM) flow with Cadence C-to-Silicon Compiler for its next-generation multimedia system-on-chip (SoC) design. The Cadence TLM approach and technology help Sunplus boost design team productivity and control development costs while ensuring high-quality chips for their TV, set-top box, and DVD offerings.

By deploying transaction-level modeling with Cadence C-to-Silicon Compiler, which delivers high-level synthesis, Sunplus engineers can design and verify their chips at a higher level of abstraction. This enables them to explore more architectural options and more quickly re-target IP to satisfy various performance, power consumption, and cost needs.

"In order to accelerate system development time, we decided to adopt the Cadence C-to-Silicon Compiler for our next product because it can generate the best quality of results," said Cheng-Yuh Wu, director of DVD IC Design Division I at Sunplus. "In addition, C-to-Silicon Compiler, as part of a TLM flow, helps our engineering teams optimize their designs early in the design cycle, including power characteristics. Perhaps most important, we can use a more abstract language -- SystemC -- than traditional Verilog/VHDL to do our design. This translates into shorter development time for complex designs, with higher IP reuse for subsequent end products."

As a key element of the Cadence system realization offerings, the TLM flow provides a connected path from system development down to silicon realization. This TLM-driven flow is scalable, greatly improving verification productivity and enabling more IP re-use, saving time and costs. Additionally, the open flow is standards-based, with Cadence C-to-Silicon Compiler reading in designs described in the IEEE1666™ SystemC standard.

"TLM design and verification continues to grow in importance and industry use as time-to-market pressures mount in the highly competitive consumer electronics markets," said Jack Erickson, director, product marketing, System Realization at Cadence. "The Cadence TLM flow with the C-to-Silicon Compiler is currently helping many leading semiconductor and system companies, including Sunplus, tackle the challenges of today's complex system designs. This open, connected, and scalable approach to system realization delivers significantly faster turnaround time for the development and re-use of complex designs -- and delivers on the EDA360 vision."

The selection of the Cadence TLM flow over other vendors' point products is the latest in a series of Sunplus Technology working closely with Cadence to deliver innovative complex products.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. IEEE 1666 is a trademark of the IEEE. All other trademarks are the property of their respective owners.

Contact Information

  • For more information, please contact:
    Dean Solov
    Cadence Design Systems, Inc.