SOURCE: Verific Design Automation

June 12, 2017 11:00 ET

Verific Acquires INVIO Platform from Invionics Software

Rapid Application Development Platform will be added to Verific's Parser Platform

ALAMEDA, CA--(Marketwired - Jun 12, 2017) - Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry, today announced it acquired the INVIO product line from Invionics Software.

Under terms of the agreement, Verific will acquire Invionics Software's entire INVIO technology portfolio, for electronic design automation (EDA) tools and flows. An R&D group with real-world design experience and a deep understanding of EDA software development will join Verific's engineering department.

The move enables Verific users to simplify and streamline their design environment, while reducing cost and accelerating chip development. The Invionics platform is language agnostic and offers the higher level of abstraction semiconductor company CAD support departments need for their SystemVerilog and VHDL flows.

By combining technologies and expertise, Verific will provide a high-level, easy-to-use and scriptable interface called INVIO with Invionics Software's 100 high-level application programming interfaces (APIs) to its Parser Platform of approximately 2,000 low-level SystemVerilog and VHDL APIs.

"We're pleased to be able to offer our users added capabilities with the INVIO APIs to accelerate their next EDA product or custom tool development," remarks Rob Dekker, Verific's founder and chief technology officer.

"Verific and Invionics have been partners for several years and work well together," comments Jim Derbyshire, Invionics Software's chairman and chief executive officer, who will not join Verific. "Together, they will become a powerhouse able to accelerate design tool and flow developments throughout the semiconductor and system design industry."

Verific will be at the Design Automation Conference (DAC) in Booth #639 June 19-21 from10 a.m. until 6 p.m. at the Austin Convention Center in Austin, Texas. Contact Rick Carlson at (970) 948 9650 or rick@verific.com for more information. Verific is co-sponsor of "Verified," a new DAC party with a verification theme presented by OneSpin to be held Tuesday from 8 p.m. until 1 a.m. at Easy Tiger. A limited number of tickets for both are available at the Verific booth.

Verific's SystemVerilog, VHDL and UPF parsers are in production and development flows throughout semiconductor companies worldwide, from emerging companies to established Fortune 500 vendors. Applications range from analysis, simulation, formal verification and synthesis to emulation and virtual prototyping, in-circuit debug and design for test. Verific distributes its Parser Platforms as C++ source code and compile on all 32 and 64 bit Unix, Linux, Mac and Windows operating systems.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups to develop advanced electronic design automation (EDA) products quickly and cost effectively. Since 1999, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555.

Engage with Verific at:
Email: info@verific.com
Website: www.verific.com
LinkedIn: https://www.linkedin.com/company-beta/810695
Facebook: https://www.facebook.com/Verific-Design-Automation-100448363329771/

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

Contact Information

  • For more information, contact:
    Nanette Collins
    Public Relations for Verific
    (617) 437-1822
    Email Contact