SOURCE: Verific

January 21, 2014 07:30 ET

Verific Design Automation Ends 2013 With Double-Digit Revenue Increase

Longtime Customers Include Biggest Names in EDA, IDMs Who Recognize Quality Software, Service

ALAMEDA, CA--(Marketwired - Jan 21, 2014) - Verific Design Automation, provider of SystemVerilog, Verilog and VHDL parsers, closed 2013 with a double-digit increase in revenue and 56 active user companies, many of whom are longstanding customers.

2013 also marked the year that Verific shipped its 100th license since its inception in 1999.

"We attribute our success to a few basic principles," remarks Michiel Ligthart, Verific's president and chief operating officer, who notes that the corporate goal is to provide the best architected and implemented front-ends in the industry. "We encourage our R&D and customer support teams to operate as a seamless extension of our users' teams to ensure outstanding software quality and service."

Verific customers include some of the biggest names in both electronic design automation (EDA) companies, such as Aldec, Atrenta, Forte, Jasper, Real Intent, Mentor and Synopsys, and integrated device manufacturers (IDMs), including AMD, Altera, Lattice, Microsemi, NVIDIA, Tabula and Xilinx.

Its software serves as the front end to a wide range of EDA and field programmable gate array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. Verific's Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl application programming interfaces (APIs). Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog and VHDL. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: www.verific.com.

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

Contact Information

  • For more information, contact:
    Nanette Collins
    Public Relations for Verific
    (617) 437-1822
    Email Contact