ALAMEDA, CA--(Marketwire - Jan 28, 2013) - Verific Design Automation (www.verific.com), provider of SystemVerilog, Verilog and VHDL parsers, ended 2012 with 52 active user companies and a revenue increase of 20% over 2011.
"Much of our business in 2012 came as a result of our reputation for quality, reliable software and excellent customer service, the hallmarks of our corporate culture," says Michiel Ligthart, Verific's president and chief operating officer. "EDA developers continue to select our parsers so that they can focus on their core competencies and get their products to market more efficiently."
In 2012, Verific signed six new licensed customers in a mix that includes both electronic design automation (EDA) companies and integrated device manufacturers (IDMs). Several existing customers added further software to their existing product mix.
Verific's software serves as the front end to a wide range of EDA and field programmable gate array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. The Verific Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl application programming interfaces (APIs). Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog and VHDL. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: firstname.lastname@example.org. Website: www.verific.com.
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