ALAMEDA, CA and VANCOUVER, BC--(Marketwire - November 16, 2010) - Verific Design Automation and Veridae Systems jointly announced today that the Verific front-end software has been licensed to Veridae for inclusion in the new Clarus family of debug and validation products.
Verific's Verilog analyzer and static elaborator is a platform for parsing the IEEE Verilog standard, allowing Clarus to work with a comprehensive internal representation of a register transfer level (RTL) design rather than the original Verilog language. Verific's tools are tightly integrated with the Clarus family, technology based upon research activity at the University of British Columbia (UBC).
The Clarus family of products provides unprecedented visibility into complex systems on chip (SoCs), field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs) at all stages of validation, allowing engineers to quickly pinpoint and understand unexpected behaviors, correct problems, and rapidly move devices into production. Debug problems that previously required weeks, or even months, can be resolved in hours.
Veridae chose Verific based on its reputation in the electronic design automation (EDA) and semiconductor community as the supplier of de facto standard front-end software for hardware description language (HDL) design. In addition to supplying the front-end software, Verific's founder and President Rob Dekker provided support on the best technical approaches to interfacing the Verific software with the Clarus tools.
"We really enjoy working with Verific," remarks Dr. Brad Quinton, Veridae's chief technical officer and founder. "Their software and support is excellent. By leveraging Verific's software, we have been able to focus on developing the key value-add technologies for our customers."
Adds Dekker: "It's been a pleasure for us to watch Veridae move from its early stages of development to introducing the Clarus family. It gives us great satisfaction to know we've played a part in the product launch."
About Veridae Systems Inc.
Veridae Systems Inc. provides innovative debug and validation technology that enables engineers to bring complex ICs from prototype to production while realizing significant savings in both cost and time to market. Veridae is privately held, with technology spun out of research activity at the University of British Columbia (UBC). The company was founded in 2009, and has corporate headquarters at #201-1545 West 8th Avenue, Vancouver, BC, V6J 1T5. More information is available on the web at: http://www.veridae.com/
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard front-end software supporting SystemVerilog, Verilog and VHDL design. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: www.verific.com.
Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
Contact Information:
For more information, contact:
Nanette Collins
Public Relations for Verific
(617) 437-1822