SOURCE: Verific Design Automation

May 19, 2011 10:00 ET

Verific Unveils Perl Interface for Its SystemVerilog, VHDL Front-End Solutions

Will Demonstrate Full Product Line During Design Automation Conference

ALAMEDA, CA--(Marketwire - May 19, 2011) - Verific Design Automation, long known for its SystemVerilog and VHDL front-end solutions used by leading EDA, FPGA and semiconductor companies worldwide, today unveiled a Perl interface to its industry-standard, IEEE-compliant SystemVerilog and VHDL parsers and elaborators.

"We get strong interest for our parser technology from ASIC and FPGA design engineers looking to solve a specific problem in their RTL code or netlist," says Rob Dekker, Verific's founder and chief technology officer. "These engineers are not necessarily C++ programmers and would prefer to put a solution together using a scripting language. It's for this group of users that we created our Verific Perl module."

All 2,000 Verific's standard C++ application programming interfaces (APIs) and supporting functionality, such as iterators, have been exported to a Verific Perl module included in a Perl program through a standard Perl use clause.

The Perl interface will be released to existing licensees in the June 2011 release.

Verific will demonstrate the SystemVerilog and VHDL Perl APIs, along with the rest of its product line, in Booth #2733 at the at the 48th Design Automation Conference (DAC) June 6-8 at the San Diego Convention Center in San Diego, Calif.

A white paper discussing details of the application is available for download at the Verific website found at:

Since its founding in 1999, Verific's software has served as the front end to a wide range of EDA and FPGA tools for analysis, simulation, verification, synthesis, emulation and test of RTL designs. Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard front-end solutions supporting SystemVerilog, Verilog and VHDL design. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Website:

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

Contact Information

  • For more information, contact:
    Nanette Collins
    Public Relations for Verific
    (617) 437-1822
    Email Contact