SOURCE: Verific

August 25, 2011 11:00 ET

vSync Circuits Licenses Verific Design Automation's Parser Platform

Integrates HDL Front-End Solutions With Clock Domain Crossing Verification

ALAMEDA, CA--(Marketwire - Aug 25, 2011) - Verific Design Automation, supplier of industry-standard, IEEE-compliant hardware description language (HDL) front-end solutions, today announced vSync Circuits Ltd. in Israel has licensed its parser platform for use with the vSync clock domain crossing (CDC) verification software.

Verific's SystemVerilog and VHDL parsers have been tightly integrated with vSync Circuits' vChecker, software to statically verify a complete, multi-clock domain design.

"We had an excellent experience with the integration of Verific's front-end tools into our tools," remarks Reuven Dobkin, chief technology officer of vSync Circuits. "Full-scale integration took us one month, thanks both to Verific technology and Verific support. We have found Verific to be a professional and the most advanced company in the field. The fast integration, allowed us to significantly shorten the time to market for our products."

Adds Michiel Ligthart, Verific's chief operating officer: "vSync Circuits has taken a unique approach to solving synchronization failures in multiple clock domain designs. It gives us great pleasure to be part of this solution."

Unlike typical CDC verification tools, the vSync Circuits suite focuses on providing the correct solutions, rather than merely pointing at the problems. Currently, vSync Circuits' software -- vChecker and vGenerator, a synchronizer customized for each interface and each clock domain crossing -- is in use with multiple design teams worldwide.

Since its founding in 1999, Verific's software has served as the front end to a wide range of EDA and FPGA tools for analysis, simulation, verification, synthesis, emulation and test of RTL designs. Its industry-standard, IEEE-compliant SystemVerilog and VHDL parsers and elaborators now include a Perl interface. Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard front-end solutions supporting SystemVerilog, Verilog and VHDL design. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Website:

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

Contact Information

  • For more information, contact:
    Nanette Collins
    Public Relations for Verific
    (617) 437-1822
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